1. Field of the Invention
The present invention relates to a master slice semiconductor integrated circuit, and in particular to a master slice semiconductor integrated circuit which has a clock tree structure formed by a dedicated fixed wiring layer.
2. Description of the Related Art
In general, a logic circuit includes combinational circuits which are constituted by gates and the like, and sequential circuits such as flip-flops or latches which take in a signal in synchronization with an edge or a level of a clock signal. Circuit connection of these combinational circuits and sequential circuits is different depending upon customer specifications.
Conventionally, in order to efficiently manufacture an semiconductor integrated circuit corresponding to the logic circuit of the customer specifications, a wafer for master slice, which is processed up to a manufacturing process common to customer specifications by regularly arranging a basic cell repeatedly in an internal region, is manufactured in advance. Then, according to a customer request, in a customized wiring process, a gate, a flip-flop, and the like are constituted and connected by wirings of a customized wiring layer, which is automatically wired on the basis of the customer specifications, to manufacture a master slice semiconductor integrated circuit for the respective customer specifications.
In this case, naturally, the number of sequential circuits and an arrangement thereof in the logic circuit are different depending upon the customer specifications. Clock skew, which is a delay difference among clock inputs of the respective sequential circuits, occurs due to a distance from a clock input terminal to the clock input of the respective sequential circuits or a length of a clock wiring. When this clock skew reaches or exceeds a predetermined value, some sequential circuits start to malfunction, and the logic circuit as a whole malfunctions. In particular, in the case in which the respective sequential circuits operate on the basis of multiphase clock signals, malfunction due to clock skew among the multiphase clock signals are more likely to occur.
In order to avoid the malfunction due to clock skew, various clock signal distribution circuits have been used in a master slice semiconductor integrated circuit so as to have low clock skew. For example, FIG. 1 is an arrangement diagram showing an example of arrangement of a clock distribution circuit in a chip of a master slice semiconductor integrated circuit. (see: JP-A-2003-152082) Here, clock wirings in the clock distribution circuit are collectively shown as a bus wiring.
This master slice semiconductor integrated circuit includes the clock distribution circuit in an internal region where cells 3 dedicated for combinational circuits and cells 2 dedicated for sequential circuits are arranged alternately by a unit of column and connected by wirings of a customized wiring layer on the basis of customer specifications. This clock distribution circuit, considering that an entire internal region is a highest order divided region A1, hierarchically divides the internal region into four equally. A selector 1, selectors 21 to 24, and selectors 301 to 316, which select clock signals and also operate as clock buffers, are embedded and arranged in divided regions A1, A21 to A24, and A301 to A316 of three hierarchies from the highest order (A1) to the lowest order (A301 to A316). In addition, output wirings of these selectors 1, 21 to 24, and 301 to 316 are branched in a tree shape by wirings of a fixed wiring layer dedicated for a clock wiring in advance. Clock signals CK1 to CK8 of eight phases of an external input are selectively distributed to the cells 2 dedicated for sequential circuits of the lowest order divided regions A301 to A316 from four directions in the circumference.
FIG. 2 is a circuit diagram showing an example of the clock distribution circuit in this master slice semiconductor integrated circuit. This clock distribution circuit includes twenty-one selectors 1, 21 to 24, and 301 to 316 which are connected in a cascade pattern of three stages in a tree shape in association with the respective divided regions A1, A21 to A24, and A301 to A316 of the highest order to lowest order three hierarchies.
The selector 1 is in the highest stage and includes eight multiplexers which are inputted with clock signals CK1 to CK8 of eight phases from the outside and select one of the clock signals. These eight multiplexers are divided into two groups, each of which consists of four multiplexers. Each group of the multiplexers outputs total four phases of clock signals to two selectors 21 and 23 or 22 and 24 of the next stage through a bus.
The two selectors 21 and 23 include four multiplexers, which are inputted with four phases of clock signals divided and outputted for each group from the selector 1 of the former stage, and select one of the clock signals, respectively. The four multiplexers of the selector 21 are divided into two groups, each of which consists of two multiplexers. Each group of the multiplexers outputs total two phases of clock signals to the two selectors 301 and 303 or 302 and 304 of the next stage through a bus. In addition, the four multiplexers of the selector 23 are divided into two groups, each of which consists of two multiplexers. Each group of the multiplexers outputs total two phases of clock signals to the two selectors 309 and 311 or 310 and 312 of the next stage through a bus.
Similarly, the two selectors 22 and 24 include four multiplexers, which are inputted with four phases of clock signals divided and outputted for each group from the selector 1 of the former stage, and select one of the clock signals, respectively. The four multiplexers of the selector 22 are divided into two groups, each of which consists of two multiplexers. Each group of the multiplexers outputs total two phases of clock signals to the two selectors 305 and 307 or 306 and 308 of the next stage through a bus. In addition, the four multiplexers of the selector 24 are divided into two groups, each of which consists of two multiplexers. Each group of the multiplexers outputs total two phases of clock signals to the two selectors 313 and 315 or 314 and 316 of the next stage through a bus.
The sixteen selectors 301 to 316 are in the lowest stage. The selectors 301 to 316 include a multiplexer, which is inputted with two phases of clock signals divided and outputted for each group from the four selectors 21 to 24 of the former stage, select one of the clock signals, and output the clock signal to the cells 2 dedicated for sequential circuits of the lowest order divided regions A301 to A316, respectively. For example, the two selectors 301 and 303 are inputted with two phases of clock signals divided and outputted from the selector 21 of the former stage, select one of the clock signals, and output the clock signal to the cells 2 dedicated for sequential circuits of the lowest order divided regions A301 and A303, respectively. The other selectors 303 to 316 operate in the same manner as a group of two, and output a clock signal to the cells dedicated for a sequential circuit of the divided regions A303 to A316 of the lowest order, respectively.
In addition, all the multiplexers constituting the above-described each selector can select one of input clock signals on the basis of a control signal. As the control signal, a potential of a power supply or the ground is supplied to the respective multiplexers according to the wirings of the customized wiring layer.
Therefore, the clock distribution circuit in this conventional master slice semiconductor integrated circuit can select inputs of clock signals, which are required in the respective lower divided regions, in the respective selector of each stage connected in a cascade pattern in a tree shape in association with the respective divided regions of the respective hierarchies of the highest to lowest orders. In addition, the clock distribution circuit can select an arbitrary clock signal from multiphase clock signals on the basis of customer specifications and distribute the clock signal to the cells 2 dedicated for sequential circuits of the lowest order. Further, output wirings of the respective selectors are branched in an equal load and an equal wiring length in a tree shape according to the wirings of the dedicated fixed wiring layer, and the multiphase clock signals are distributed at an equal delay from the selectors of the first stage to the cells 2 dedicated for sequential circuits of the respective divided regions of the lowest order. Since this equal delay distribution of the clock signals is performed with high accuracy according to a master slice design, clock skew is reduced.
As described above, circuit connection of logic circuits is different depending upon customer specifications, and a ratio of sequential circuits and the number of phases of clock signals required for the sequential circuits are also different.
On the other hand, in the case in which the ratio of the sequential circuits of the logical circuit is small, in general, the conventional mater slice semiconductor integrated circuit can constitute the sequential circuits using a part of the divided regions, which are hierarchically divided equally, and can connect the entire logic circuit. However, even in the other divided regions which do not constitute the sequential circuits, clock signals are sequentially distributed to the cells dedicated for sequential circuits by the clock distribution circuit, the respective selectors operate, and clock wirings formed by dedicated fixed wirings repeat charge and discharge at a clock frequency. Since the clock frequency is a highest frequency, power consumption by charge and discharge of respective node of the clock distribution circuit is generally large. In addition, there is a problem in that the power consumption of the clock distribution circuit depends upon the master slice design, and is not proportional to a size of a the logic circuit of customer design and always takes a maximum value.
Further, in the conventional master slice semiconductor integrated circuit, a circuit area in the part of the clock distribution circuit increases exponentially with respect to not only an increase in the number of hierarchies of equal division but also an increase in the number of phases of clock signals which can be distributed. Practically, there is a problem in that the number of phases of clock signals cannot be increased so much, a range of application of the master slice semiconductor integrated circuit is small, and it is impossible to flexibly cope with an increase in the number of phases of clock signals due to a change in customer specifications or the like.